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M66596FP 데이터시트(PDF) 76 Page - Renesas Technology Corp |
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M66596FP 데이터시트(HTML) 76 Page - Renesas Technology Corp |
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76 / 131 page ![]() M66596FP/WG rev .1.00 2006.3.14 page 76 of 127 3.4 Buffer memory This chapter explains operation about the buffer memory which this controller contains. When there is no description, both a Host and Peripheral are the same operation. 3.4.1 Buffer memory allocation Figure 3.19 shows an example of a buffer memory map for the controller. The buffer memory is an area shared by the user system control CPU and the controller. In the buffer memory status, there are times when the access right to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to the controller (SIE side). The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise one block, and the memory areas are set using the first block number of the number of blocks (specified using the BUFNMB and BUFSIZE bits of the PIPEBUF register). Moreover, three FIFO ports are used for access to the buffer memory (reading and writing data). A pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE bit of the C/DxFIFOSEL register. The buffer statuses of the various pipes can be confirmed using the BSTS bit of the DCPCTR register and PIPExCTR register. Also, the access right of the FIFO port can be confirmed using the FRDY bit of the C/DxFIFOCTR register. FIFO Port D0FIFO Port BUFNMB=0, BUFSIZE=3 CFIFO Port D1FIFO Port CURPIPE=1 CURPIPE=3 Buffer memory PIPEBUF reg PIPE0 PIPE6 PIPE7 PIPE5 PIPE1 PIPE2 PIPE3 PIPE4 BUFNMB=4, BUFSIZE=0 BUFNMB=5, BUFSIZE=0 BUFNMB=6, BUFSIZE=3 BUFNMB=10, BUFSIZE=7 BUFNMB=18, BUFSIZE=3 BUFNMB=22, BUFSIZE=7 BUFNMB=28, BUFSIZE=2 CURPIPE=6 Figure 3.19 Example of buffer memory map |
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