SH7261 datasheet(76/1348 Pages) RENESAS

76 / 1348 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 44 of 1312

REJ09B0320-0200

Classification

Types

Operation

Code

Function

No. of

Instructions

AND

Logical AND

NOT

Bit inversion

Logical OR

TAS

Memory test and bit set

TST

Logical AND and T bit set

Logic

operations

XOR

Exclusive OR

Shift

ROTL

One-bit left rotation

ROTR

One-bit right rotation

ROTCL

One-bit left rotation with T bit

ROTCR

One-bit right rotation with T bit

SHAD

Dynamic arithmetic shift

SHAL

One-bit arithmetic left shift

SHAR

One-bit arithmetic right shift

SHLD

Dynamic logical shift

SHLL

One-bit logical left shift

SHLLn

n-bit logical left shift

SHLR

One-bit logical right shift

SHLRn

n-bit logical right shift

Branch

Conditional branch, conditional delayed branch

(branch when T = 0)

Conditional branch, conditional delayed branch

(branch when T = 1)

BRA

Unconditional delayed branch

BRAF

Unconditional delayed branch

BSR

Delayed branch to subroutine procedure

BSRF

Delayed branch to subroutine procedure

JMP

Unconditional delayed branch

JSR

Branch to subroutine procedure

Delayed branch to subroutine procedure

RTS

Return from subroutine procedure

Delayed return from subroutine procedure

RTV/N

Return from subroutine procedure with Rm

→

R0 transfer

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