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SH7261 데이터시트(PDF) 77 Page - Renesas Technology Corp |
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SH7261 데이터시트(HTML) 77 Page - Renesas Technology Corp |
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77 / 1348 page ![]() Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 45 of 1312 REJ09B0320-0200 Classification Types Operation Code Function No. of Instructions 14 CLRT T bit clear 36 CLRMAC MAC register clear System control LDBANK Register restoration from specified register bank entry LDC Load to control register LDS Load to system register NOP No operation RESBANK Register restoration from register bank RTE Return from exception handling SETT T bit set SLEEP Transition to power-down mode STBANK Register save to specified register bank entry STC Store control register data STS Store system register data TRAPA Trap exception handling 19 FABS Floating-point absolute value 48 Floating-point instructions FADD Floating-point addition FCMP Floating-point comparison FCNVDS Conversion from double-precision to single- precision FCNVSD Conversion from single-precision to double- precision FDIV Floating-point division FLDI0 Floating-point load immediate 0 FLDI1 Floating-point load immediate 1 FLDS Floating-point load into system register FPUL FLOAT Conversion from integer to floating-point FMAC Floating-point multiply and accumulate operation FMOV Floating-point data transfer FMUL Floating-point multiplication FNEG Floating-point sign inversion |
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