SH7261 datasheet(108/1348 Pages) RENESAS

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Section 3 Floating-Point Unit (FPU)

Rev. 2.00 Sep. 07, 2007 Page 76 of 1312

REJ09B0320-0200

These possibilities are shown in the individual instruction descriptions. All exception events that

originate in the FPU are assigned as the same exception event. The meaning of an exception is

determined by software by reading from FPSCR and interpreting the information it contains. If no

bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V are

set in the FPU exception enable field, this indicates that an actual exception source is not

generated. Also, the destination register is not changed by any FPU exception handling operation.

Except for the above, the FPU disables exception handling. In every processing, the bit

corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the

operation result.

• Invalid operation (V): qNaN is generated as the result.

• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.

• Overflow (O):

When rounding mode = RZ, the maximum normalized number, with the same sign as the

unrounded value, is generated.

When rounding mode = RN, infinity with the same sign as the unrounded value is generated.

• Underflow (U):

Zero with the same sign as the unrounded value is generated.

• Inexact exception (I): An inexact result is generated.

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