HD6432351 datasheet(339/1025 Pages) RENESAS

339 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 305 of 988

REJ09B0330-0300

On-chip

supporting

module

IRQ interrupt

DTVECR

Interrupt controller

CPU

DTC

DTCER

Clear

controller

Select

Interrupt

request

Source flag cleared

Clear

Clear request

Interrupt mask

Figure 8.3 Block Diagram of DTC Activation Source Control

When an interrupt has been designated a DTC activation source, existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

8.3.3

DTC Vector Table

Figure 8.4 shows the correspondence between DTC vector addresses and register information.

Table 8.4 shows the correspondence between activation, vector addresses, and DTCER bits. When

the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0]

<< 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector

address is H'0420.

The DTC reads the start address of the register information from the vector address set for each

activation source, and then reads the register information from that start address. The register

information can be placed at predetermined addresses in the on-chip RAM. The start address of

the register information should be an integral multiple of four.

The configuration of the vector address is the same in both normal and advanced modes, a 2-byte

unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip

RAM.

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