HD6432351 datasheet(347/1025 Pages) RENESAS

전자부품 데이터시트 검색엔진

ALLDATASHEET.CO.KR

HD6432351 데이터시트(PDF) 347 Page - Renesas Technology Corp

부품명	HD6432351

상세설명	16-Bit Single-Chip Microcomputer

PDF	1025 Pages

Scroll/Zoom	100%

제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

Logo

347 / 1025 page

Section 8 Data Transfer Controller (DTC)

Rev. 3.00 Sep 15, 2006 page 313 of 988

REJ09B0330-0300

8.3.8

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 8.9 shows the memory map for chain transfer.

Source

Destination

DTC vector

address

start address

CHNE = 1

CHNE = 0

Figure 8.9 Chain Transfer Memory Map

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ]
Alldatasheet는? \| 광고문의 \| 운영자에게 연락하기 \| 개인정보취급방침 \| 링크 투 데이터시트 \| 링크교환 \| 제조사별 검색 All Rights Reserved©Alldatasheet.com
Mirror Sites English : Alldatasheet.com \| English : Alldatasheet.net \| Chinese : Alldatasheetcn.com \| German : Alldatasheetde.com \| Japanese : Alldatasheet.jp Russian : Alldatasheetru.com \| Korean : Alldatasheet.co.kr \| Spanish : Alldatasheet.es \| French : Alldatasheet.fr \| Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com \| Polish : Alldatasheet.pl \| Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in \| Mexican : Alldatasheet.com.mx \| British : Alldatasheet.co.uk \| New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com \| icmetro.com

ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ]

Family Site : ic2ic.com | icmetro.com