HD6432351 datasheet(243/1025 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 209 of 988

REJ09B0330-0300

7.2.5

DMA Band Control Register (DMABCR)

FAE1

R/W

FAE0

R/W

—

R/W

—

R/W

DTA1

R/W

—

R/W

—

R/W

DTA0

R/W

Bit

DMABCRH

Initial value

R/W

DTME1

R/W

DTE1

R/W

DTME0

R/W

DTE0

R/W

DTIE1B

R/W

DTIE0A

R/W

DTIE1A

R/W

DTIE0B

R/W

Bit

DMABCRL

Initial value

R/W

DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC

channel.

DMABCR is initialized to H'0000 by a reset, and in standby mode.

Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short

address mode or full address mode.

In short address mode, channels 1A and 1B are used as independent channels.

Bit 15

FAE1

Description

Short address mode

(Initial value)

Full address mode

Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short

address mode or full address mode.

In short address mode, channels 0A and 0B are used as independent channels.

Bit 14

FAE0

Description

Short address mode

(Initial value)

Full address mode

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