HD64F2149YV datasheet(419/1075 Pages) RENESAS

419 / 1075 page

Section 13 Timer Connection

Rev. 3.00 Jan 18, 2006 page 391 of 1044

REJ09B0280-0300

Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits

select the signal source for the CLO signal (clamp waveform).

Bit 6

Bit 1

Bit 0

ISGENE

CLMOD1

CLMOD2

Description

The CL1 signal is selected

(Initial value)

The CL2 signal is selected

The CL3 signal is selected

The CL4 signal is selected

13.2.4

Edge Sense Register (SEDGR)

Bit

Initial value

Read/Write

Notes: 1. Only 0 can be written, to clear the flags.

2. The initial value is undefined since it depends on the pin states.

VEDG

R/(W)

HEDG

R/(W)

CEDG

R/(W)

HFEDG

R/(W)

VFEDG

R/(W)

IVI

—*2

PREQF

R/(W)

IHI

—*2

SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection

input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI

signals.

The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The

initial value of the lower 2 bits is undefined, since it depends on the pin states.

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