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M16C/1N 데이터시트(PDF) 54 Page - Renesas Technology Corp

부품명 M16C/1N
상세설명  RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES
PDF  238 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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M16C/1N 데이터시트(HTML) 54 Page - Renesas Technology Corp

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Rev.1.00
Oct 20, 2004
page 42 of 222
M16C/1N Group
9. Bus Control
REJ09B0007-0100Z
9. Bus Control
During access, the memory areas (ROM, RAM, FLASH, etc.) and the SFR area have different bus cycles.
The memory areas can be accessed in one cycle of the CPU operation clock BCLK. The SFR area can be
accessed in two cycles of BCLK.
Software wait states can be inserted to the memory areas by using the PM17 bit of the processor mode
register 1 (bit 7 at address 000516) (Note 1). When the PM17 bit is set to "0", the memory areas are
accessed in one cycle of BCLK. When the PM17 bit is set to "1", the memory areas are accessed in two
cycles of BCLK. The PM17 bit is "0" after the reset status is cancelled. The SFR area is not influenced by
the PM17 bit and is always accessed in two cycles of BCLK.
The Table 9.1 lists bus cycle for access areas. Figure 9.1 shows SFR area and memory areas.
Note 1: When rewriting the processor mode register 1, set the PRC1 bit of the protect register (bit 1 at
address 000A16) to "1".
0000016
XXXXX16
FFFFF16
0040016
YYYYY16
Internal ROM area
SFR area
(For details, refer to
4. SFR)
Internal RAM area
SFR area
Memory area
Table 9.1 Bus cycle for access areas
Figure 9.1 SFR area and memory areas
Area
SFR
Internal
ROM/RAM
PM17
0
Bus cycle
2 BCLK cycles
1 BCLK cycle
12 BCLK cycles



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