M16CSLASH1N datasheet(77/238 Pages) RENESAS

77 / 238 page

Rev.1.00

Oct 20, 2004

page 65 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

Address match interrupt enable register

Symbol

AIER

Address

000916

When reset

XXXXXX002

Function

Bit name

Bit symbol

AIER0

Address match interrupt register i (i = 0, 1)

Symbol

RMAD0

RMAD1

When reset

XXXX00002, 000000002, 000000002

Address

001216 to 001016

001616 to 001416

Function

Values that can be set

Address setting register for address match interrupt

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read,

turns out to be indeterminate.

0000016 to FFFFF16

Address match interrupt 0

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

AIER1

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read,

turns out to be indeterminate.

Address match interrupt 1

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

b0 b7

(b19)

(b16)

(b15)

(b8)

(b23)

b5 b4

10.6 Address Match Interrupt

An address match interrupt is generated immediately before the instruction at the address indicated by

the address match interrupt register is executed. Two address match interrupts can be set, each of which

can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not

affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the

program counter (PC) for an address match interrupt varies depending on the instruction being executed.

Figure 10.16 shows the address match interrupt-related registers.

Figure 10.16 Address match interrupt-related registers

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