M16CSLASH1N datasheet(66/238 Pages) RENESAS

66 / 238 page

Rev.1.00

Oct 20, 2004

page 54 of 222

M16C/1N Group

10. Interrupt

REJ09B0007-0100Z

10.1.5.5 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is ac-

cepted to the instant the interrupt routine is executed — is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when

the execution of the instruction is completed, and transfers control to the interrupt sequence from

the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or

RMPA instruction, the processor temporarily suspends the instruction being executed, and trans-

fers control to the interrupt sequence.

In the interrupt sequence, the processor carries out the following in sequence given:

(1) CPUgets the interrupt information (the interrupt number and interrupt request level) by reading

address 0000016. After this, the corresponding interrupt request bit becomes "0".

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt

sequence in the temporary register (Note 1) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (Dflag), and the stack pointer select flag (U

______

flag) to "0" (the U flag, however, does not change if the INT instruction, in software interrupt

numbers 32 through 63, is executed).

(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the

first address of the interrupt routine.

Note 1: This register cannot be utilized by the user.

Figure 10.4 shows the time required for executing interrupt sequence.

Indeterminate

The indeterminate segment is dependent on the queue buffer.

If the queue buffer is ready to take an instruction, a read cycle occurs.

Indeterminate

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

Interrupt

information

Address

0000016

Indeterminate

SP-2

SP-4

vec

vec+2

BCLK

Address bus

Data bus

Figure 10.4 Time required for executing interrupt sequence

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