M16CSLASH1N datasheet(127/238 Pages) RENESAS

127 / 238 page

Rev.1.00

Oct 20, 2004

page 115 of 222

M16C/1N Group

13. Serial I/O

REJ09B0007-0100Z

• Example of transmit timing (when internal clock is selected)

• Example of receive timing (when external clock is selected)

Tc = TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f1, f8, f32, fc)

n: value set to BRGi

Transfer clock

Transmit enable

bit (TE)

Transmit buffer

empty flag (Tl)

CLKi

TxDi

Transmit

flag (TXEPT)

"0"

"1"

"0"

"1"

"0"

"1"

The above timing applies to the following settings:

Internal clock is selected.

CLK polarity select bit = 0.

Transmit interrupt cause select bit = 0.

Transmit interrupt

request bit (IR)

"0"

"1"

1 / fEXT

Dummy data is set in UARTi transmit buffer register

Transmit enable

bit (TE)

Transmit buffer

empty flag (Tl)

CLKi

RxDi

Receive complete

flag (Rl)

"0"

"1"

"0"

"1"

"0"

"1"

Receive enable

bit (RE)

"0"

"1"

Receive data is taken in

Transferred from UARTi transmit buffer register to UARTi transmit register

Read out from UARTi receive buffer register

The above timing applies to the following settings:

External clock is selected.

CLK polarity select bit = 0.

fEXT: frequency of external clock

Transferred from UARTi receive register

to UARTi receive buffer register

Receive interrupt

request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Meet the following conditions when the CLKi input level

before data reception = "H"

Transmit enable bit

"1"

Receive enable bit

"1"

Dummy data write to UARTi transmit buffer register

Shown in ( ) are bit symbols.

Cleared to "0" when interrupt request is accepted, or cleared by software

TCLK

Stopped pulsing because transfer enable bit = "0"

Data is set in UARTi transmit buffer

Transferred from UARTi transmit buffer register to UARTi transmit

Cleared to "0" when interrupt request is accepted, or cleared by software

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

Figure 13.7 Typical transmit/receive timings in clock synchronous serial I/O mode

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