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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M16C/1N 데이터시트(PDF) 132 Page - Renesas Technology Corp |
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M16C/1N 데이터시트(HTML) 132 Page - Renesas Technology Corp |
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132 / 238 page  Rev.1.00 Oct 20, 2004 page 120 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Transmit enable bit (TE) Transmit buffer empty flag (TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi The above timing applies to the following settings : Parity is enabled. One stop bit. Transmit interrupt cause select bit = 1. "1" "0" "1" "0" "1" Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Cleared to "0" when interrupt request is accepted, or cleared by software Transmit enable bit (TE) Transmit buffer empty flag (TI) TxDi Transmit register empty flag (TXEPT) "0" "1" "0" "1" "0" "1" The above timing applies to the following settings : Parity is disabled. Two stop bits. Transmit interrupt cause select bit = 0. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D0 D1 D2 D3 D4 D5 D6 D7 ST P SP Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register D0 D1 D2 D3 D4 D5 D6 D7 ST P SP D0 D1 ST Stopped pulsing because transmit enable bit = "0" Start bit Data is set in UARTi transmit buffer register D0 D1 D2 D3 D4 D5 D6 D7 ST SP D8 D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 ST SPSP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register. "0" SP Cleared to "0" when interrupt request is accepted, or cleared by software Figure 13.12 Typical transmit timings in UART mode |
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