M16CSLASH1N datasheet(165/238 Pages) RENESAS

165 / 238 page

Rev.1.00

Oct 20, 2004

page 153 of 222

M16C/1N Group

16. CAN Module

REJ09B0007-0100Z

16.12.2 Transmission

Figure 16.25 shows the timing of the transmit sequence.

TrmActive

CANbus

TrmReq

Succ. Xmit Int.

MBOX

TrmSucc

TrmState

SentData

SOF

Transmission slot No.

B(4)

ACK

EOF

IFS

(1)

(3)

(2)

(1)

i=0 to15

Figure 16.25 Timing of Transmit Sequence

(1) If the TrmReq bit of the C0MCTLi register (i=0 to 15) is set to "1" (Transmission slot) in bus idle

state, the TrmActive bit of the C0MCTLi register and the TrmState bit of the C0STR register are set

to "1" (Transmitting/Transmitter), and the CAN module starts transmitting.

(2) If the arbitration is lost after the CAN module starts transmitting, the TrmActive and TrmState bits

are set to "0".

(3) If the transmission is successful without lost arbitration, the SentData bit of the C0MCTLi register is

set to "1" (Transmission is successfully completed) and TrmActive bit of the C0MCTLj register is

set to "0" (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits of

the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is gen-

erated and the MBOX (the slot number which transmitted the message) and TrmSucc bits of the

C0STR register are changed.

(4) When starting the next transmission, set the SentData and TrmReq bits to "0", then set the TrmReq

bit to "1" after checking that the SentData and TrmReq bits are set to "0".

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