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M16C/1N 데이터시트(PDF) 194 Page - Renesas Technology Corp

부품명 M16C/1N
상세설명  RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES
PDF  238 Pages
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제조업체  RENESAS [Renesas Technology Corp]
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M16C/1N 데이터시트(HTML) 194 Page - Renesas Technology Corp

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Rev.1.00
Oct 20, 2004
page 182 of 222
M16C/1N Group
19. Flash Memory Version
REJ09B0007-0100Z
Flash memory control register 1
Symbol
Address
After reset
FMR1
01B516
0000XX0X2
b7
b6
b5
b4
b3
b2 b1
b0
Bit symbol
Bit name
Function
EW1 mode select bit
(Note 1)
0 : EW0 mode
1 : EW1 mode
FMR11
0
Reserved bit
Set to "0"
Reserved bit
The value in this bit when read is
indeterminate.
Reserved bit
Set to "0"
0
0
RW
RO
RW
Block 0-3 rewrite enable bit
(Note 2)
0 : Disables rewriting
1 : Enables rewriting
FMR16
RW
RW
RW
(b0)
(b5-b4)
(b7)
Reserved bit
The value in this bit when read is
indeterminate.
(b3-b2)
RO
Note 1: When setting this bit to "1", write a "0" and then a "1" in succession while the FMR01 bit is "1". Make sure no
interrupts will occur before completion of these two write operations.
The FMR01 and FMR11 bits both are cleared to "0" by setting the FMR01 bit to "0".
Note 2: When setting this bit to "1", write a "0" and then a "1" to it in succession while the FMR01 bit is "1". Make sure
no interrupts will occur before completion of these two write operations.
Flash memory control register 4
Symbol
Address
After reset
FMR4
01B316
010000002
b7
b6
b5
b4
b3
b2 b1
b0
Bit symbol
Bit name
Function
Suspend request bit (Note 2)
0 : Erase restart
1 : Suspend request
FMR41
0
Reserved bit
Set to "0"
00
0
0
RW
RW
Suspend enable bit (Note 1)
0 : Invalid
1 : Valid
FMR40
RW
Suspend status
0 : Erase active
1 : Erase inactive
(erasure-suspend)
FMR46
RO
Set to "0"
RO
RW
(b7)
Reserved bits
(b5-b2)
Note 1: When setting this bit to "1", write a "0" and then a "1" to it in succession. Make sure no interrupts will occur
before completion of these two write operations.
Note 2: This bit is valid only when the FMR40 bit is "1" and can be written in only the period from issuing an erase
command until completion of erasing.
• In EW0 mode, this bit can be set to "0" or "1" by program.
• In EW1 mode, this bit is automatically set to "1" when a maskable interrupt occurs during erasure execution
while the FMR40 bit is "1". It can not be set to "1" by program. (Writing "0" is available.)
Figure 19.5 FMR1 Register, FMR4 Register



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