M16CSLASH1N datasheet(205/238 Pages) RENESAS

205 / 238 page

Rev.1.00

Oct 20, 2004

page 193 of 222

M16C/1N Group

19. Flash Memory Version

REJ09B0007-0100Z

19.5.6 Full Status Check

When an error occurs, the FMR0 register's FMR06 to FMR07 bits are set to "1", indicating occurrence

of each specific error. Therefore, execution results can be verified by checking these status bits (full

status check).

Table 19.6 lists errors and FMR0 register status. Figure 19.12 shows a full status check flowchart and

the action to be taken when each error occurs.

Table 19.6 Errors and FMR0 register status

FRM00 register

(status register)

status

Error

Error occurrence condition

FMR07

FMR06

(SR5)

(SR4)

Command

• When any command is not written correctly

sequence error • When invalid data was written other than those that can be writ-

ten in the second bus cycle of the block erase command (i.e.,

other than 'xxD016' or 'xxFF16') (Note 1)

Erase error

• When the block erase command was executed on locked blocks

but the blocks were not automatically erased correctly.

Program error

• When the program command was executed on unlocked blocks

but the blocks were not automatically programmed correctly.

Note 1: Writing 'xxFF16' in the first bus cycle places the microcomputer in read array mode.

Simultaneously, the command code written in the first cycle becomes invalid.

M16C/1N 데이터시트(PDF) 205 Page - Renesas Technology Corp