SH7052 datasheet(356/919 Pages) RENESAS

356 / 919 page

330

• Bit 2—Noise Canceler Enable (NCE): Enables or disables the noise canceler function.

Bit 2: NCE

Description

Noise canceler function is disabled

(Initial value)

Noise canceler function is enabled

• Bits 1 and 0—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10

external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s).

Bit 1: CKEG1

Bit 0: CKEG0

Description

TI10 input disabled

(Initial value)

TI10 input rising edges detected

TI10 input falling edges detected

TI10 input rising and falling edges both detected

Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates

the occurrence of channel 10 input capture or compare-match.

Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is

enabled by the corresponding bit in timer interrupt enable register 10 (TIER10).

TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software

standby mode.

Bit:

——

———

—

Initial value:

R/W:

Bit:

——

CMF10G CMF10B ICF10A CMF10A

Initial value:

R/W:

R/(W)*

Note: * Only 0 can be written, to clear the flag.

• Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0.

SH7052 데이터시트(PDF) 356 Page - Renesas Technology Corp