SH7052 datasheet(93/919 Pages) RENESAS

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5.3

Address Errors

5.3.1

Address Error Sources

Address errors occur when instructions are fetched or data read or written, as shown in table 5.6.

Table 5.6

Bus Cycles and Address Errors

Bus Cycle

Type

Bus

Master

Bus Cycle Description

Address Errors

Instruction

CPU

Instruction fetched from even address

None (normal)

fetch

Instruction fetched from odd address

Address error occurs

Instruction fetched from other than on-chip

peripheral module space*

None (normal)

Instruction fetched from on-chip peripheral

module space*

Address error occurs

Instruction fetched from external memory

space when in single chip mode

Address error occurs

Data

CPU or

Word data accessed from even address

None (normal)

read/write

DMAC

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

Byte or word data accessed in on-chip

peripheral module space*

None (normal)

Longword data accessed in 16-bit on-chip

peripheral module space*

None (normal)

Longword data accessed in 8-bit on-chip

peripheral module space*

Address error occurs

External memory space accessed when in

single chip mode

Address error occurs

Note: * See section 8, Bus State Controller, for details of the on-chip peripheral module space.

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