SH7052 datasheet(96/919 Pages) RENESAS

96 / 919 page

5.5

Exceptions Triggered by Instructions

5.5.1

Types of Exceptions Triggered by Instructions

Exception processing can be triggered by trap instructions, general illegal instructions, and illegal

slot instructions, as shown in table 5.9.

Table 5.9

Types of Exceptions Triggered by Instructions

Type

Source Instruction

Comment

Trap instructions

TRAPA

Illegal slot

instructions

Undefined code placed

immediately after a delayed

branch instruction (delay slot)

and instructions that rewrite

the PC

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF

General illegal

instructions

Undefined code anywhere

besides in a delay slot

5.5.2

Trap Instructions

When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The exception service routine start address is fetched from the exception processing vector

table that corresponds to the vector number specified in the TRAPA instruction. That address

is jumped to and the program starts executing. The jump that occurs is not a delayed branch.

SH7052 데이터시트(PDF) 96 Page - Renesas Technology Corp