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SH7052 데이터시트(PDF) 418 Page - Renesas Technology Corp |
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SH7052 데이터시트(HTML) 418 Page - Renesas Technology Corp |
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418 / 919 page ![]() 392 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set. The timing in this case is shown in figure 10.69. Pø DMAC clear request signal Input capture/ compare-match signal Interrupt status flag ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D Interrupt status flag clear signal Figure 10.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match |
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