SH7052 datasheet(441/919 Pages) RENESAS

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12.1.4

Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the

WDT mode, and control the reset signal.

Table 12.2

WDT Registers

Address

Name

Abbreviation

R/W

Initial Value

Write*

Read*

Timer control/status

TCSR

R/(W)*

H'18

H'FFFFEC10

Timer counter

TCNT

R/W

H'00

H'FFFFEC11

Reset control/status

RSTCSR

R/(W)*

H'1F

H'FFFFEC12

H'FFFFEC13

Notes: 1. Write by word transfer. These registers cannot be written in byte or longword.

2. Read by byte transfer. These registers cannot be read in word or longword.

3. Only 0 can be written to bit 7 to clear the flag.

4. In register access, three cycles are required for both byte access and word access.

12.2

12.2.1

Timer Counter (TCNT)

TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more

difficult to write to. See section 12.2.4, Register Access, for details.) When the timer enable bit

(TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts

counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR.

When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow

signal (

WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected

in the WT/

IT bit of TCSR.

TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and

when the TME bit is cleared to 0.

Bit:

Initial value:

R/W:

R/W

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