SH7052 datasheet(466/919 Pages) RENESAS

466 / 919 page

440

• Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin

(external)

• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full

interrupts can start the direct memory access controller (DMAC) to transfer data.

• Selection of LSB-first or MSB-first transfer (8-bit length)

This selection is available regardless of the communication mode. (The descriptions in this

section are based on LSB-first transfer.)

14.1.2

Block Diagram

Figure 14.1 shows a block diagram of the SCI.

Parity

generation

Parity check

Transmit/

receive control

Baud rate

generator

Clock

External clock

Internal

data bus

RxD

RDR

TDR

RSR

TSR

SSR

SCR

SMR

SDCR

BRR

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

SCK

RSR:

RDR:

TSR:

TDR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

SMR:

SCR:

SSR:

BRR:

SDCR:

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial direction control register

TxD

SCI

Module data bus

Figure 14.1 SCI Block Diagram

SH7052 데이터시트(PDF) 466 Page - Renesas Technology Corp

SH7052 데이터시트(HTML) 466 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL