SH7052 datasheet(521/919 Pages) RENESAS

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14.4

SCI Interrupt Sources and the DMAC

The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full

(RXI), and transmit-data-empty (TXI). Table 14.12 lists the interrupt sources and indicates their

priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial

control register (SCR). Each interrupt request is sent separately to the interrupt controller.

TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access

controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes

data in the transmit data register (TDR).

RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data.

RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR).

ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC.

TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the

TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the

transmit operation is complete.

Table 14.12 SCI Interrupt Sources

Interrupt Source

Description

DMAC Activation

Priority

ERI

Receive error (ORER, PER, or FER)

High

RXI

Receive data full (RDRF)

Yes

TXI

Transmit data empty (TDRE)

Yes

TEI

Transmit end (TEND)

Low

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