SH7052 datasheet(127/919 Pages) RENESAS

127 / 919 page

101

7.1.3

The UBC has the six registers shown in table 7.1. Break conditions are established using these

registers.

Table 7.1

Name

Abbr.

R/W

Initial

Value

Address*

Access

Size

User break address register H

UBARH

R/W

H'0000

H'FFFFEC00

8, 16, 32

User break address register L

UBARL

R/W

H'0000

H'FFFFEC02

8, 16, 32

User break address mask register H

UBAMRH

R/W

H'0000

H'FFFFEC04

8, 16, 32

User break address mask register L

UBAMRL

R/W

H'0000

H'FFFFEC06

8, 16, 32

User break bus cycle register

UBBR

R/W

H'0000

H'FFFFEC08

8, 16, 32

User break control register

UBCR

R/W

H'0000

H'FFFFEC0A 8, 16, 32

Note: * In register access, three cycles are required for byte access and word access, and six

cycles for longword access.

7.2

7.2.1

User Break Address Register (UBAR)

UBARH:

Bit:

UBA31

UBA30

UBA29

UBA28

UBA27

UBA26

UBA25

UBA24

Initial value:

R/W:

R/W

Bit:

UBA23

UBA22

UBA21

UBA20

UBA19

UBA18

UBA17

UBA16

Initial value:

R/W:

R/W

SH7052 데이터시트(PDF) 127 Page - Renesas Technology Corp

SH7052 데이터시트(HTML) 127 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL