SH7052 datasheet(209/919 Pages) RENESAS

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183

Table 10.3

ATU-II Registers (cont)

Channel

Name

Abbrevia-

tion

R/W

Initial

Value

Address

Access Size (Bits)

Timer interval interrupt

request register 2B

ITVRR2B

R/W

H'00

H'FFFFF428

Timer I/O control

TIOR0

R/W

H'00

H'FFFFF42A

Timer status register 0

TSR0

R/(W)* H'0000 H'FFFFF42C 16

Timer interrupt enable

TIER0

R/W

H'0000 H'FFFFF42E

Free-running counter

TCNT1A

R/W

H'0000 H'FFFFF440

Free-running counter

TCNT1B

R/W

H'0000 H'FFFFF442

General register 1A

GR1A

R/W

H'FFFF H'FFFFF444

General register 1B

GR1B

R/W

H'FFFF H'FFFFF446

General register 1C

GR1C

R/W

H'FFFF H'FFFFF448

General register 1D

GR1D

R/W

H'FFFF H'FFFFF44A

General register 1E

GR1E

R/W

H'FFFF H'FFFFF44C

General register 1F

GR1F

R/W

H'FFFF H'FFFFF44E

General register 1G

GR1G

R/W

H'FFFF H'FFFFF450

General register 1H

GR1H

R/W

H'FFFF H'FFFFF452

Output compare

OCR1

R/W

H'FFFF H'FFFFF454

Offset base register 1

OSBR1

H'0000 H'FFFFF456

Timer I/O control

TIOR1A

R/W

H'00

H'FFFFF459

8, 16

Timer I/O control

TIOR1B

R/W

H'00

H'FFFFF458

Timer I/O control

TIOR1C

R/W

H'00

H'FFFFF45B

Timer I/O control

TIOR1D

R/W

H'00

H'FFFFF45A

Timer control register

TCR1A

R/W

H'00

H'FFFFF45D

Timer control register

TCR1B

R/W

H'00

H'FFFFF45C

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