전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

SH7052 데이터시트(PDF) 288 Page - Renesas Technology Corp

부품명 SH7052
상세설명  SuperHTM RISC engine
PDF  919 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 데이터시트(HTML) 288 Page - Renesas Technology Corp

Back Button SH7052 Datasheet HTML 284Page - Renesas Technology Corp SH7052 Datasheet HTML 285Page - Renesas Technology Corp SH7052 Datasheet HTML 286Page - Renesas Technology Corp SH7052 Datasheet HTML 287Page - Renesas Technology Corp SH7052 Datasheet HTML 288Page - Renesas Technology Corp SH7052 Datasheet HTML 289Page - Renesas Technology Corp SH7052 Datasheet HTML 290Page - Renesas Technology Corp SH7052 Datasheet HTML 291Page - Renesas Technology Corp SH7052 Datasheet HTML 292Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 288 / 919 page
background image
262
• Bit 2—Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by
the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 2: ICE0C
Description
0
ICI0C interrupt requested by ICF0C is disabled
(Initial value)
1
ICI0C interrupt requested by ICF0C is enabled
• Bit 1—Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by
the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 1: ICE0B
Description
0
ICI0B interrupt requested by ICF0B is disabled
(Initial value)
1
ICI0B interrupt requested by ICF0B is enabled
• Bit 0—Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by
the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 0: ICE0A
Description
0
ICI0A interrupt requested by ICF0A is disabled
(Initial value)
1
ICI0A interrupt requested by ICF0A is enabled
Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B)
TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and
overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
8
——
——
———
OVE1A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
IME1H
IME1G
IME1F
IME1E
IME1D
IME1C
IME1B
IME1A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com