SH7708 datasheet(150/633 Pages) RENESAS

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7.2.11

Break Control Register (BRCR)

Bit:

Bit name:

CMFA

CMFB

—

PCBA

—

Initial value:

R/W:

R/W

Bit:

Bit name:

DBEB

PCBB

—

SEQ

—

Initial value:

R/W:

R/W

The break control register (BRCR) is a 16-bit read/write register that controls user breaks.

BRCR:

1. Determines whether to use channels A and B as two independent channels or as sequential

conditions.

2. Selects whether to break before or after instruction execution during the instruction fetch cycle.

3. Determines whether to include the BDRB register in the channel B comparison conditions.

It also has a condition-match flag. A power-on or manual reset initializes BRCR to H'0000.

Bit 15—Condition Match Flag A (CMFA): Set to 1 when the break conditions set in channel A are

met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.

Bit 15: CMFA

Description

Channel A break conditions do not match.

(Initial value)

Channel A break conditions match.

Bit 14—Condition Match Flag B (CMFB): Set to 1 when the break conditions set in channel B are

met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.

Bit 14: CMFB

Description

Channel B break conditions do not match.

(Initial value)

Channel B break conditions match.

Bits 13 to 11—Reserved: These bits always read 0. The write value should always be 0.

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