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7721 데이터시트(PDF) 80 Page - Renesas Technology Corp |
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7721 데이터시트(HTML) 80 Page - Renesas Technology Corp |
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80 / 577 page ![]() CLOCK GENERATING CIRCUIT 7721 Group User’s Manual 5–3 5.2 Clocks 5.2 Clocks Figure 5.2.1 shows the clock generating circuit block diagram. Fig. 5.2.1 Clock generating circuit block diagram Q XIN XOUT 1/2 R S Q R S Q R S 1 CPU 1/8 1/2 f2 1/2 1/8 f16 f64 f512 f32 f512 Interrupt request STP instruction Reset WIT instruction Ready request CPU wait request from BIU Operation clock for internal peripheral devices Watchdog timer CPU : Central Processing Unit BIU : Bus Interface Unit Watchdog timer frequency select bit : Bit 0 at address 6116 Note: This signal is generated when the watchdog timer’s most significant bit becomes “0.” (Note) Watchdog timer frequency select bit “0” “1” Bus request DRAMC Hold DMAC |
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