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CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–7

Fig. 5.3.1 Stop mode terminating sequence by interrupt request occurrence

(2)

Termination by hardware reset

______

Supply “L” level to the RESET pin by using the external circuit until the oscillation of the oscillator

is stabilized.

The CPU and the SFR area are initialized in the same way as system reset. However, the internal

RAM area retains the same contents as that before executing the STP instruction. The terminating

sequence is the same as the internal processing sequence which is performed after reset.

Refer to “CHAPTER 4. RESET” for details about reset.

5.3 Stop mode

CPU

“7FF16”

“FFF16”

Stop mode

f(XIN)

Operating

Stopped

Internal peripheral devices

Operating

Value of Watchdog timer

f32 ! 2048 counts

Interrupt request

used to terminate

Stop mode

(Interrupt request bit)

Stopped

Operating

qInterrupt request used to

terminate Stop mode

occurs.

qOscillation starts.(When

an external clock is input

from the XIN pin, clock

input starts.)

qWatchdog timer starts

counting.

qSTP instruction

is executed

qWatchdog timer’s MSB = “0”

(However, watchdog timer interrupt

request does not occur.)

qSupply of CPU,

starts.

qInterrupt request which has been used

to terminate Stop mode is accepted.

CPU

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