7721 datasheet(106/577 Pages) RENESAS

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7721 Group User’s Manual

7–9

INTERRUPTS

7.4 Interrupt priority level

When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected

at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they

are accepted in order of priority levels. In other words, the interrupt request with the highest priority level

is accepted first.

Among a total of 23 interrupt sources, the user can set the desired priority levels for 20 interrupt sources

except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.

Use the interrupt priority level select bits to set their priority levels. Priority levels of reset, which is handled

as the interrupt request with the highest priority, and the watchdog timer interrupt are set by hardware.

Figure 7.4.1 shows the interrupt priority set by hardware.

Note that software interrupts are not affected by the interrupt priority levels. Whenever the instruction is

executed, a program certainly branches to the interrupt routine.

7.4 Interrupt priority level

Watchdog

timer

Reset

20 interrupt sources except software interrupts

and watchdog timer interrupt

The user can set the desired priority levels inside of the dotted line.

Priority levels determined by hardware

High

Low

Priority level

••••••••••••••••••

Fig. 7.4.1 Interrupt priority level set by hardware

7721 데이터시트(PDF) 106 Page - Renesas Technology Corp