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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7721 데이터시트(PDF) 127 Page - Renesas Technology Corp |
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7721 데이터시트(HTML) 127 Page - Renesas Technology Corp |
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127 / 577 page  TIMER A 7721 Group User’s Manual 8–8 8.2 Block description 8.2.5 Port P5 direction register The I/O pins of Timers A2 to A4 are multiplexed with port P5. When using these pins as Timer Aj’s input pins, set the corresponding bits of the port P5 direction register to “0” to set these port pins for the input mode. When used as Timer Aj’s output pins, these pins are forcibly set to the output pins of Timer Aj regardless of the direction registers’s contents. Figure 8.2.5 shows the relationship between the port P5 direction register and the Timer Aj’s I/O pins. Bit Bit name Functions 0 1 2 3 4 5 6 7 TA2OUT pin TA3OUT pin TA3IN pin 0 : Input mode 1 : Output mode When using these pins as Timer Aj’ s input pins, set the corresponding bits to “0.” Port P5 direction register (Address D16) b1 b0 b2 b3 b4 b5 b6 b7 TA2IN pin At reset RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW : Bits 6 and 7 are not used for Timer A. TA4OUT pin TB0IN pin TB1IN pin TA4IN pin Fig. 8.2.5 Relationship between port P5 direction register and Timer Aj’s I/O pins |
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