7721 datasheet(139/577 Pages) RENESAS

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TIMER A

7721 Group User’s Manual

8–20

8.4 Event counter mode

Fig. 8.4.1 Structures of timer Aj mode register and timer Aj register in event counter mode

00 1

Bit

Up-down switching factor select

bit

Count polarity select bit

Bit name

These bits are invalid in event counter mode.

Fix this bit to “0” in event counter mode.

Functions

0 : Counts at falling edge of external signal

1 : Counts at rising edge of external signal

0 : Contents of up-down register

1 : Input signal to TAjOUT pin

At reset

Pulse output function select bit

Operating mode select bits

0 : No pulse output (TAjOUT pin functions

as a programmable I/O port.)

1 : Pulse output (TAjOUT pin functions

as a pulse output pin.)

0 1 : Event counter mode

b1 b0

Timer Aj mode register (j = 2 to 4) (Addresses 5816 to 5A16)

(b15)

(b8)

Timer A2 register (Addresses 4B16, 4A16)

Timer A3 register (Addresses 4D16, 4C16)

Timer A4 register (Addresses 4F16, 4E16)

15 to 0

Bit

Functions

At reset

These bits can be set to “000016” to “FFFF16.”

Assuming that the set value = n, the counter

divides the count source frequency by (n + 1)

during countdown, or by (FFFF16 – n + 1)

during countup.

When reading, the register indicates the

counter value.

Undefined

Note: Read from or write to this register in a unit of 16 bits.

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