| 전자부품 데이터시트 검색엔진 |
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7721 데이터시트(PDF) 182 Page - Renesas Technology Corp |
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7721 데이터시트(HTML) 182 Page - Renesas Technology Corp |
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182 / 577 page ![]() TIMER B 7721 Group User’s Manual 9–15 9.4 Event counter mode Fig. 9.4.1 Structures of timer Bj mode register and timer Bj register in event counter mode b7 b0 b7 b0 (b15) (b8) Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) RW 15 to 0 Bit Functions At reset RW These bits can be set to “000016” to “FFFF16.” Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Undefined Note: Read from or write to this register in a unit of 16 bits. 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Counts at both falling and rising edges of external signal 1 1 : Do not select. b7 b6 b5 b4 b3 b2 b1 b0 01 Bit Count polarity select bits Bit name These bits are invalid in event counter mode. This bit is invalid in event counter mode; its value is undefined at reading. 7 Functions At reset 0 0 0 RW Operating mode select bits 1 0 1 : Event counter mode b1 b0 0 0 0 !! 0 2 RW RW 3 4 5 6 RW RW — RW RW Timer Bj mode register (j = 0, 1) (Addresses 5B16, 5C16) b3 b2 Nothing is assigned. ! Undefined Undefined RO |
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