7721 datasheet(296/577 Pages) RENESAS

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7721 Group User’s Manual

13-17

DMA CONTROLLER

13.2 Block description

13.2.13 DMAi interrupt control register

Figure 13.2.9 shows the structure of the DMAi interrupt control register. For details about interrupts, refer

to “CHAPTER 7. INTERRUPTS.”

DMAi interrupt control register (i = 0 to 3) (Addresses 6C16 to 6F16)

Bit

7 to 4

Interrupt request bit

Bit name

At reset

Functions

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

0 : No interrupt requested

1 : Interrupt requested

Interrupt priority level

select bits

–

Undefined

Nothing is assigned.

Low level

High level

Fig. 13.2.9 Structure of DMAi interrupt control register

(1)

Interrupt priority level select bits (bits 2 to 0)

These bits select a DMAi interrupt’s priority level. When using DMAi interrupts, select one of the

priority levels (1 to 7). When a DMAi interrupt request occurs, its priority level is compared with the

processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level

is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”)

To disable DMAi interrupts, set these bits to “0002” (level 0).

(2)

Interrupt request bit (bit 3)

This bit is set to “1” when a DMAi interrupt request occurs after the DMA transfer is complete. This

bit is automatically cleared to “0” when the DMAi interrupt request is accepted. This bit can be set

to “1” or cleared to “0” by software.

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