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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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7733 데이터시트(PDF) 377 Page - Renesas Technology Corp |
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7733 데이터시트(HTML) 377 Page - Renesas Technology Corp |
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377 / 940 page  CLOCK GENERATING CIRCUIT 7733 Group User’s Manual 14–14 14.3.3 Clock transition Figure 14.3.9 shows the clock transition. 14.3 Clock control Fig. 14.3.9 Clock transition Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating System clock: Sub clock Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Sub clock Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Main clock Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 – f512 (Note 2) Internal clock φ : Stopped Wait mode Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped f2 – f512 (Note 2) Internal clock φ : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped System clock: Main clock WIT instruction Interrupt request generated Port-Xc selection bit: “1” STP instruction Reset System clock selection bit: “1” (Note 1) System clock selection bit: “0” (Note 1) Main clock stop bit: “1” Stop mode Main clock stop bit: “0” WIT instruction WIT instruction WIT instruction STP instruction STP instruction Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated Interrupt request generated g For the stop and wait modes, refer to chapter “11. STOP AND WAIT MODES.” Notes 1: Before selecting the system clock, make sure that operation of the oscillator is fully stabilized. Additionally, generate oscillation stabilizing time by software. 2: In the wait mode, whether clocks f2 to f512 are supplied or stopped can be specified by the system clock stop bit at wait state. STP instruction Interrupt request generated Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped |
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