7733 datasheet(68/940 Pages) RENESAS

68 / 940 page

represents that bits 2 to 7 are not used for selecting a processor mode.

CENTRAL PROCESSING UNIT (CPU)

7733 Group User’s Manual

2–29

Table 2.5.2 Method of selecting processor mode

2.5 Processor modes

Processor mode

Single-chip mode

Memory expansion mode

Microprocessor mode

Pin CNVSS’s level

VSS (0 V) (Note 1)

VCC (5 V) (Note 2)

Processor mode bits

Notes 1: The microcomputer starts operating in the single-chip mode after reset. By setting the processor

mode bits, the processor mode of the microcomputer can be switched from the single-chip mode

to the other modes.

2: The microcomputer starts operating in the microprocessor mode after reset. The microcomputer

cannot operate in the other modes. Accordingly, so fix the processor mode bits (bits 1 and 0 at

address 5E16) to “102.”

Fig. 2.5.4 Structure of processor mode register 0

Bit

Bit name

Functions

At reset

Processor mode bits

Wait bit

Software reset bit

Must be fixed to “0.”

Clock

f 1 output selection bit

(Note 2)

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Microprocessor mode

1 1: Do not select.

0: Software wait is inserted when

accessing external area.

1: No software wait is inserted

when accessing external area.

Microcomputer is reset by

setting this bit to “1.”

This bit is “0” at reading.

0 0: 7 cycles of

0 1: 4 cycles of

1 0: 2 cycles of

1 1: Do not select.

0: Clock

f 1 output is disabled.

(P42 functions as a

1: Clock

f 1 output is enabled.

functions as a clock

f 1 output pin.)

b1 b0

b5 b4

Processor mode register 0 (address 5E16)

(Note 1)

Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset.

(When read, this bit is always “0.”)

2: This bit is ignored in the microprocessor mode. (It may be “0” or “1.”)

Interrupt priority detection

time selection bits

(Port P42

programmable I/O port.)

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