7733 datasheet(398/940 Pages) RENESAS

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ELECTRICAL CHARACTERISTICS

7733 Group User’s Manual

15–19

15.10 Memory expansion mode and Microprocessor mode : with wait 0

Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless

otherwise noted)

g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted.

tw(H)

tw(L)

tsu(D–E)

th(E–D)

Min.

Limits

Unit

External clock input cycle time (Note 2)

External clock input high-level pulse width (Note 3)

External clock input low-level pulse width (Note 3)

External clock rise time

External clock fall time

Data input setup time

Data input hold time

Parameter

Max.

Symbol

Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns.

3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values

from 0.45 through 0.55.

Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1),

unless otherwise noted)

Unit

Limits

Max.

Data formula (Min.)

Min.

130

3 ! 109

2! f(f2)

3 ! 109

2! f(f2)

1 ! 109

2! f(f2)

2 ! 109

2! f(f2)

2 ! 109

2! f(f2)

1 ! 109

2! f(f2)

1 ! 109

2! f(f2)

– 33

– 45

– 22

– 23

– 35

– 25

– 30

Symbol

td(An–E)

td(A–E)

th(E–An)

tw(ALE)

tsu(A–ALE)

th(ALE–A)

td(ALE–E)

td(E–DQ)

th(E–DQ)

tw(EL)

tpxz(E–DZ)

tpzx(E–DZ)

td(BHE–E)

td(R/W–E)

th(E–BHE)

th(E–R/W)

td(E–

φ 1)

Parameter

Address output delay time

Address hold time

ALE pulse width

Address output setup time

Address hold time

ALE output delay time

Data output delay time

Data hold time

pulse width

Floating start delay time

Floating release delay time

BHE

output delay time

R/W output delay time

BHE

hold time

R/W hold time

φ 1 output delay time

Conditions

Fig. 15.11.1

Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.

2: f(f2) represents the clock f2 frequency.

For the relationship with the main clock and sub clock, refer to Table 14.3.1.

1 ! 109

2! f(f2)

4 ! 109

2! f(f2)

1 ! 109

2! f(f2)

3 ! 109

2! f(f2)

3 ! 109

2! f(f2)

1 ! 109

2! f(f2)

1 ! 109

2! f(f2)

– 22

– 30

– 20

– 33

– 22

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