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SERIAL I/O

7733 Group User’s Manual

8–43

8.3 Clock synchronous serial I/O mode

8.3.8 Precautions for clock synchronous serial I/O

1. The transfer clock is generated by the operation of the transmit control circuit. Accordingly, even when

performing only reception, the transmit operation (setting for transmission) must be performed. In this

case, dummy data is output from the TxDi pin to the external.

2. When an internal clock is selected during reception, the transfer clock is generated if the following

conditions are satisfied:

•The transmit enable bit is set to “1.” (Transmission is enabled.)

•Dummy data is set to the UARTi transmission buffer register.

When an external clock is selected during reception, the transfer clock is generated if the following

conditions are satisfied:

•The transmit enable bit is set to “1.”

•A clock is input to the CLKi pin after dummy data is set to the UARTi transmission buffer register.

3. When an external clock is selected, make sure that the following conditions are satisfied with the CLKi

pin’s input level = “H” if the CLK polarity selection bit = “0” or with the CLKi pin’s input level = “L” if the

CLK polarity selection bit = “1”:

[At transmitting]

Set the transmit enable bit to “1.”

Write the transmit data to the UARTi transmission buffer register.

_____

____

Input “L” level to the CTSi pin (when CTS function is selected).

[At receiving]

Set the receive enable bit to “1.”

Set the transmit enable bit to “1.”

Write dummy data to the UARTi transmission buffer register.

4. When receiving data in succession, set dummy data to the low-order byte of the UARTi transmission

buffer register each time when 1-byte data is received.

5. For performing the transmission and the reception simultaneously, UART2 does not distinguish the

transmission interrupt from the reception interrupt. The UART2 transmission/reception interrupt request

occurs when either interrupt request occurs. Accordingly, in the system which performs the transmission

and reception simultaneously for UART2, not use the UART2 transmission/reception interrupt but use

the method of poling the transmission buffer empty flag and the receive completion flag by software.

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