7733 datasheet(256/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–53

8.4.4 Transmit operation

When the transmit conditions described in section “8.4.3 Method of transmission” are satisfied, the

transfer clock is generated and the following operations are automatically performed after one cycle of the

transfer clock has passed.

q The UARTi transmission buffer register’s contents is transferred to the UARTi transmission register.

q The transmission buffer empty flag is set to “1.”

q The transmission register empty flag is cleared to “0.”

q A UARTi transmission interrupt request occurs and the interrupt request bit is set to “1.”

The transmit operation is described below.

Data in the UARTi transmission register is transmitted from the TXDi pin.

This data is transmitted bit by bit sequentially in order of ST

→DATA (LSB)→ ••• →DATA (MSB)→PAR

→SP according to the transfer data format.

In the middle of the stop bit (the second stop bit when two stop bits are selected), the transmission

conditions for the next data are satisfied or not is checked.

When the transmit conditions for the next data are satisfied at completion of transmission in operation ,

a start bit is generated following the stop bit and the next data is transmitted. When performing transmission

in succession, set the next transmit data in the UARTi transmission buffer register during transmission

(when transmission register empty flag = “0”).

When the transmit conditions for the next data are not satisfied, the TXDi pin outputs “H” level and the

transfer clock is stopped.

Figure 8.4.6 shows an example of transmit timing when the transfer data length has a 8 bits. Figure 8.4.7

shows an example of transmit timing when the transfer data length has a 9 bits.

8.4 Clock asynchronous serial I/O (UART) mode

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