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7733 데이터시트(PDF) 261 Page - Renesas Technology Corp

부품명 7733
상세설명  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 데이터시트(HTML) 261 Page - Renesas Technology Corp

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SERIAL
I/O
7733 Group User’s Manual
8–58
8.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts]
[When using interrupts]
A UARTi receive interrupt request
occurs when reception is completed.
UARTi receive interrupt
g This diagram indicates bits and registers
required for processing.
Refer to Figure 8.4.12 for details about the
change of flag status and the occurrence
timing of an interrupt request.
Processing after reading out receive data
UART0 receive buffer register (addresses 37 16, 3616)
UART1 receive buffer register (addresses 3F 16, 3E16)
UART2 receive buffer register (addresses 6B 16, 6A16)
b15
b8
Reading out the receive data
Read out the receive data
b7
b0
0
0
0
0
0
0
0
UART0 transmit/receive control register 1 (address 35 16)
UART1 transmit/receive control register 1 (address 3D 16)
UART2 transmit/receive control register 1 (address 69 16)
b7
b0
Receive completion flag
0: Reception is not completed.
1: Reception is completed.
Checking the completion of reception
1
UART0 transmit/receive control register 1 (address 35 16)
UART1 transmit/receive control register 1 (address 3D 16)
UART2 transmit/receive control register 1 (address 69 16)
b7
b0
Checking the error
Framing error flag
Parity error flag
Error sum flag
0: No error is detected.
1: Error is detected.
1
UART0 transmit/receive control register 1 (address 35 16)
UART1 transmit/receive control register 1 (address 3D 16)
UART2 transmit/receive control register 1 (address 69 16)
b7
b0
Checking the error
Overrun error flag
0: No error is detected.
1: Error is detected.
1
Fig. 8.4.10 Processing after reception is completed



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