7733 datasheet(324/940 Pages) RENESAS

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STOP AND WAIT MODES

7733 Group User’s Manual

11–17

11.4.3 Wait mode terminating operation by interrupt request occurrence

When an interrupt request occurs with supply of clocks f2 to f512 stopped, the clock supply restarts.

Supply of internal clock

φ starts.

The interrupt request which occurs in is accepted.

An interrupt which can be used for termination depends on the state of clocks f2 to f512 in the wait mode.

(Refer to Table 11.4.3.)

Table 11.4.3 Interrupts which can be used for termination of wait mode

11.4 Wait mode

Conditions for each function which generates

interrupt request

Interrupt

When the key input interrupt function is selected

____

INT2

interrupt: When the key input interrupt function is invalid.

Enabled only when the

external clock is selected

Disabled

When timer B2 functions as the clock timer

Disabled

Key input interrupt

____

INTi

interrupt (i = 0 to 2)

Timer Ai interrupt (i = 0 to 4)

Timer Bi interrupt (i = 0 to 2)

UARTi transmission interrupt (i = 0 to 2)

UARTi reception interrupt (i = 0 to 2)

Clock timer*

(timer B2) interrupt

A-D conversion interrupt

When clocks f2 to f512 are not stopped

In the event counter mode

Enabled in all modes

Always enabled

f(XIN)/32

f(XCIN)/32

Enabled in one-shot mode

and single sweep mode

Clock timer∗: Refer to section “7.6 Clock timer.”

g For each interrupt, refer to chapters “4. INTERRUPTS,” “5. KEY INPUT INTERRUPT FUNCTION,”

“6. TIMER A,” “7. TIMER B,” “8. SERIAL I/O,” and “9. A-D CONVERTER.”

Before executing the WIT instruction, be sure to enable an interrupt which is used for termination.

Also make sure that the interrupt priority level of an interrupt which is used for termination is higher than

the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed. Furthermore,

when multiple interrupts in Table 11.4.3 are enabled, the wait mode is terminated by the interrupt request

which occurs first.

11.4.4 Wait mode terminating operation by hardware reset

The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM

area retains the same contents as that before the WIT instruction was executed. The terminating sequence

is the same as the internal processing sequence after reset.

When determining whether hardware reset was applied for termination of the wait mode or system reset

was applied, use software after reset.

For reset, refer to chapter “13. RESET.”

When clocks f2 to f512 are stopped

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