TMS320VC33 datasheet(42/57 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

interrupt response timing

The following table defines the timing parameters for the INTx signals.

timing requirements for INT3−INT0 response (see Figure 29)

VC33-120

VC33-150

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

tsu(INT-H1L)

Setup time, INT3− INT0 before H1 low

th(H1L-INT)

Hold time, INT3− INT0 after H1 low

tw(INT)

Pulse duration, interrupt to ensure only one interrupt

P+5†

1.5P

2P−5†

P+5†

1.5P

2P−5†

† P = tc(H)

The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The

TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of

H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The

CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.

For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set

up and held such that a logic-low condition occurs for:

D A minimum of one H1 falling edge

D No more than two H1 falling edges

D Interrupt sources whose edges cannot be ensured to meet the H1 falling edge setup and hold times must

be further restricted in pulse width as defined by tw(INT) (parameter 51) in the table above.

When EDGEMODE=1, the falling edge of the INT0−INT3 pins are detected using synchronous logic (see

Figure 7). The pulse low and high time should be two CPU clocks or greater.

The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has

been cleared.

If the specified timings are met, the exact sequence shown in Figure 29 occurs; otherwise, an additional delay

of one clock cycle is possible.

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