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TMS320VC33 데이터시트(PDF) 34 Page - Texas Instruments

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부품명 TMS320VC33
상세설명  DIGITAL SIGNAL PROCESSOR
PDF  57 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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TMS320VC33 데이터시트(HTML) 34 Page - Texas Instruments

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TMS320VC33
DIGITAL SIGNAL PROCESSOR
SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing requirements for XF0 and XF1 when executing LDFI or LDII (see Figure 22)
VC33-120
VC33-150
UNIT
MIN
MAX
MIN
MAX
UNIT
tsu(XF1-H1L)
Setup time, XF1 before H1 low
5
4
ns
th(H1L-XF1)
Hold time, XF1 after H1 low
0
0
ns
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
LDFI or LDII (see Figure 22)
PARAMETER
VC33-120
VC33-150
UNIT
PARAMETER
MIN
MAX
MIN
MAX
UNIT
td(H3H-XF0L)
Delay time, H3 high to XF0 low
4
3
ns
H3
H1
R/W
A[23:0]
D[31:0]
RDY
XF0
XF1
Fetch
LDFI or LDII
Decode
Read
Execute
PAGEx, STRB
td(H3H-XF0L)
tsu(XF1-H1L)
th(H1L-XF1)
Figure 22. Timing for XF0 and XF1 When Executing LDFI or LDII



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