TMS320VC33 datasheet(12/57 Pages) TI

12 / 57 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PLL and clock oscillator control

The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes

control clock divide ratios, oscillator, and PLL power (see Table 1).

When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR

gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock

reference into EXTCLK, or 1−20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock

sources include:

D A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins

and EXTCLK is grounded.

D An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT

is left unconnected and XIN is grounded.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL

is a simple x5 reference multiplier with bypass and power control.

The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOPOWER), or

clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.

A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output

reference is further divided by two with clock synchronization being determined by the timing of RESET falling

relative to the present H1/H3 state.

Clock Divider

PLL

Clock and Crystal OSC

CLKMD1

CLKMD0

PLL PWR and Bypass

Oscillator Enable

C31 DIV2 Mode

LOWPOWER

MAXSPEED/

IDLE2

CPU CLOCK

1/2

X1, 1/16, Off

XOR

SEL

PLL

EXTCLK

XIN

XOUT

Figure 4. Clock Generation

Table 1. Clock Mode Select Pins

CLKMD0

CLKMD1

FEEDBACK

PLLPWR

RATIO

NOTES

Off

Fully static, very low power

Off

1/2

Oscillator enabled

Off

Oscillator enabled

2 mA @ 60 MHz, 1.8 V PLL power. Oscillator enabled

TMS320VC33 데이터시트(PDF) 12 Page - Texas Instruments

TMS320VC33 데이터시트(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

데이터시트 다운로드

링크 URL