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TMS320VC33 데이터시트(PDF) 53 Page - Texas Instruments |
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TMS320VC33 데이터시트(HTML) 53 Page - Texas Instruments |
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53 / 57 page ![]() TMS320VC33 DIGITAL SIGNAL PROCESSOR SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004 53 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 IEEE-1149.1 test access port timing The following table defines the timing parameter for the IEEE-1149.1 test access port. timing for IEEE-1149.1 test access port (see Figure 40) VC33−120 VC33−150 UNIT MIN MAX MIN MAX UNIT tsu(TMS - TCKH) Setup time, TMS / TDI to TCK high 5 5 ns th(TCKH-TMS) Hold time, TMS / TDI from TCK high 5 5 ns td(TCKL - TDOV) Delay time, TCK low to TDO valid 0 10 0 10 ns tr (TCK) Rise time, TCK 3 3 ns tf (TCK) Fall time, TCK 3 3 ns TCK TMS/TDI TDO td(TCHL-TDOV) tsu(TMS-TCKH) th(TCHK-TMS) tr(TCK) tf(TCK) Figure 40. IEEE-1149.1 Test Access Port Timings |
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