| 전자부품 데이터시트 검색엔진 |
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ATtiny5 데이터시트(PDF) 80 Page - ATMEL Corporation |
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ATtiny5 데이터시트(HTML) 80 Page - ATMEL Corporation |
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80 / 168 page ![]() 80 8127C–AVR–10/09 ATtiny4/5/9/10 This ensures that the Timer/Counter is halted and can be configured without the risk of advanc- ing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. |
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