ATmega64A datasheet(164/392 Pages) ATMEL

164 / 392 page

164

8160C–AVR–07/09

ATmega64A

19. SPI – Serial Peripheral Interface

19.1

Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

19.2

Overview

Figure 19-1. SPI Block Diagram

(1)

Note:

1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 76 for SPI pin placement.

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega64A and peripheral devices or between several AVR devices. The interconnection

between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two

Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle

when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the

data to be sent in their respective Shift Registers, and the Master generates the required clock

pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the

DIVIDER

/2/4/8/16/32/64/128

ATmega64A 데이터시트(PDF) 164 Page - ATMEL Corporation