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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATmega64A 데이터시트(PDF) 32 Page - ATMEL Corporation |
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ATmega64A 데이터시트(HTML) 32 Page - ATMEL Corporation |
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32 / 392 page  32 8160C–AVR–07/09 ATmega64A 7.6.3 XMCRB – External Memory Control Register B • Bit 7 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the Bus Keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still activated as long as XMBK is one. • Bit 6:3 – Res: Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. • Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal port pin function as described in Table 7-4. As described in “Using all Locations of External Memory Smaller than 64 KB” on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory. 7.6.4 EEARH and EEARL – EEPROM Address Register Bit 7 65 432 10 (0x6C) XMBK – – – – XMM2 XMM1 XMM0 XMCRB Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 7-4. Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins 0 0 0 8 (Full 60 KB space) None 00 1 7 PC7 0 1 0 6 PC7 - PC6 0 1 1 5 PC7 - PC5 1 0 0 4 PC7 - PC4 1 0 1 3 PC7 - PC3 1 1 0 2 PC7 - PC2 1 1 1 No Address high bits Full Port C Bit 1514131211 10 9 8 0x1F (0x3F) – – – – – EEAR10 EEAR9 EEAR8 EEARH 0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 76 543 2 1 0 Read/Write R R R R R R/W R/W R/W R/WR/W R/WR/W R/W R/W R/WR/W Initial Value 0 0 0 0 0 X X X X XXX X X X X |
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