ATmega64A datasheet(26/392 Pages) ATMEL

26 / 392 page

8160C–AVR–07/09

ATmega64A

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Conse-

quently the XMEM interface is not suited for synchronous operation.

Figure 7-6.

External Data Memory Cycles without Wait State

(1)

(SRWn1 = 0 and SRWn0 =0)

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal

or external).

Figure 7-7.

External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1

(1)

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal

or external).

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

XXXXX

XXXXXXXX

ALE

A15:8

Address

Prev. Addr.

DA7:0

Address

Data

Prev. Data

DA7:0 (XMBK = 0)

Data

Prev. Data

Address

Data

Prev. Data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

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