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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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P89LPC915FDH 데이터시트(PDF) 62 Page - NXP Semiconductors |
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P89LPC915FDH 데이터시트(HTML) 62 Page - NXP Semiconductors |
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62 / 75 page  P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 15 December 2009 62 of 75 NXP Semiconductors P89LPC915/916/917 8-bit microcontrollers with accelerated two-clock 80C51 core Table 17. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C, or −40 °C to +125 °C (see Table 3 on page 3), unless otherwise specified.[1][2] Symbol Parameter Conditions Variable clock fosc = 18 MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency industrial 7.189 7.557 7.189 7.557 MHz extended 7.004 7.741 7.004 7.741 MHz fosc(WD) internal watchdog oscillator frequency 320 520 320 520 kHz fCLKLP low power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance time P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock fosc oscillator frequency 0 18 - - MHz Tcy(clk) clock cycle time see Figure 28 55 - - - ns tCHCX clock HIGH time see Figure 28 22 Tcy(CLK) − tCLCX 22 - ns tCLCX clock LOW time see Figure 28 22 Tcy(CLK) − tCHCX 22 - ns tCLCH clock rise time see Figure 28 -5 - 5 ns tCHCL clock fall time see Figure 28 -5 - 5 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 27 16Tcy(CLK) - 888 - ns tQVXH output data set-up to clock rising edge time see Figure 27 13Tcy(CLK) - 722 - ns tXHQX output data hold after clock rising edge time see Figure 27 -Tcy(CLK) + 20 - 75 ns tXHDX input data hold after clock rising edge time see Figure 27 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 27 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄6 0 3.0 MHz master - CCLK ⁄4 - 4.5 MHz TSPICYC SPI cycle time see Figure 23, 24, 25, 26 slave 6 ⁄ CCLK - 333 - ns master 4 ⁄ CCLK - 222 - ns tSPILEAD SPI enable lead time see Figure 25, 26 slave 250 - 250 - ns tSPILAG SPI enable lag time see Figure 25, 26 250 - 250 - ns |
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